diff -ubr FreeRTOSV5.0.0/FreeRTOS/Demo/MicroBlaze/serial/serial.c FreeRTOSV5.0.0.MicroblazeISE9.1/FreeRTOS/Demo/MicroBlaze/serial/serial.c
--- FreeRTOSV5.0.0/FreeRTOS/Demo/MicroBlaze/serial/serial.c	2008-04-15 15:17:24.000000000 +0200
+++ FreeRTOSV5.0.0.MicroblazeISE9.1/FreeRTOS/Demo/MicroBlaze/serial/serial.c	2008-06-06 10:51:43.000000000 +0200
@@ -66,6 +66,10 @@
 
 /*-----------------------------------------------------------*/
 
+void vSerialISR( void *pvBaseAddress );
+
+/*-----------------------------------------------------------*/
+
 /* Queues used to hold received characters, and characters waiting to be
 transmitted. */
 static xQueueHandle xRxedChars; 
@@ -103,8 +107,10 @@
 		all the other bit settings. */
 		ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
 		ulMask |= XPAR_RS232_UART_INTERRUPT_MASK;
-		XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( ulMask ) );
-		XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 2 );
+		XIntc_mEnableIntr(XPAR_OPB_INTC_0_BASEADDR, ulMask);
+		
+		/* Register UART interrupt handler */
+		XIntc_RegisterHandler(XPAR_OPB_INTC_0_BASEADDR, XPAR_OPB_INTC_0_RS232_UART_INTERRUPT_INTR, (XInterruptHandler) vSerialISR, (void *)XPAR_RS232_UART_BASEADDR);
 	}
 	
 	return ( xComPortHandle ) 0;
diff -ubr FreeRTOSV5.0.0/FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s FreeRTOSV5.0.0.MicroblazeISE9.1/FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s
--- FreeRTOSV5.0.0/FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s	2008-04-13 18:03:42.000000000 +0200
+++ FreeRTOSV5.0.0.MicroblazeISE9.1/FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s	2008-06-06 10:51:43.000000000 +0200
@@ -4,7 +4,7 @@
 	.extern uxCriticalNesting
 	.extern pulISRStack
 
-	.global __FreeRTOS_interrupt_handler
+	.global _interrupt_handler
 	.global VPortYieldASM
 	.global vStartFirstTask
 
@@ -129,7 +129,7 @@
 	.align  2
 
 
-__FreeRTOS_interrupt_handler:
+_interrupt_handler:
 	portSAVE_CONTEXT
 	/* Entered via an interrupt so interrupts must be enabled in msr. */
 	ori r31, r31, 2
diff -ubr FreeRTOSV5.0.0/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c FreeRTOSV5.0.0.MicroblazeISE9.1/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c
--- FreeRTOSV5.0.0/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c	2008-04-15 15:17:26.000000000 +0200
+++ FreeRTOSV5.0.0.MicroblazeISE9.1/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c	2008-06-06 10:51:43.000000000 +0200
@@ -95,6 +95,11 @@
  * could have alternatively used the watchdog timer or timer 1.
  */
 static void prvSetupTimerInterrupt( void );
+
+/* 
+ * Handler for the timer interrupt.
+ */
+void vTickISR( void *pvBaseAddress );
 /*-----------------------------------------------------------*/
 
 /* 
@@ -200,17 +205,8 @@
 
 portBASE_TYPE xPortStartScheduler( void )
 {
-extern void ( __FreeRTOS_interrupt_Handler )( void );
 extern void ( vStartFirstTask )( void );
 
-
-	/* Setup the FreeRTOS interrupt handler.  Code copied from crt0.s. */
-	asm volatile ( 	"la	r6, r0, __FreeRTOS_interrupt_handler		\n\t" \
-					"sw	r6, r1, r0									\n\t" \
-					"lhu r7, r1, r0									\n\t" \
-					"shi r7, r0, 0x12								\n\t" \
-					"shi r6, r0, 0x16 " );
-
 	/* Setup the hardware to generate the tick.  Interrupts are disabled when
 	this function is called. */
 	prvSetupTimerInterrupt();
@@ -264,26 +260,26 @@
  */
 static void prvSetupTimerInterrupt( void )
 {
-XTmrCtr xTimer;
-const unsigned portLONG ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
-unsigned portBASE_TYPE uxMask;
+	const unsigned portLONG ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+	unsigned portLONG ulMask;
 
 	/* The OPB timer1 is used to generate the tick.  Use the provided library
 	functions to enable the timer and set the tick frequency. */
-	XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
-	XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
-   	XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
-	XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
-
-	/* Set the timer interrupt enable bit while maintaining the other bit 
-	states. */
-	uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
-	uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
-	XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );	
-	
-	XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
-	XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
-	XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
+	
+	/* Register handler for timer 1 */
+	XIntc_RegisterHandler(XPAR_OPB_INTC_0_BASEADDR, XPAR_OPB_INTC_0_OPB_TIMER_1_INTERRUPT_INTR, (XInterruptHandler) vTickISR, (void *)XPAR_OPB_TIMER_1_BASEADDR);
+	
+	/* Set the number of cycles the timer counts before interrupting */
+	XTmrCtr_mSetLoadReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue);
+
+	/* Enable the interrupt in the interrupt controller while maintaining 
+	all the other bit settings. */
+	ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
+	ulMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
+	XIntc_mEnableIntr(XPAR_OPB_INTC_0_BASEADDR, ulMask);
+	
+	/* Reset the timers, and clear interrupts */
+	XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK );
 }
 /*-----------------------------------------------------------*/
 
@@ -295,34 +291,8 @@
  */
 void vTaskISRHandler( void )
 {
-static unsigned portLONG ulPending;    
-
-	/* Which interrupts are pending? */
-	ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
-
-	if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
-	{
-		static XIntc_VectorTableEntry *pxTablePtr;
-		static XIntc_Config *pxConfig;
-		static unsigned portLONG ulInterruptMask;
-
-		ulInterruptMask = ( unsigned portLONG ) 1 << ulPending;
-
-		/* Get the configuration data using the device ID */
-		pxConfig = &XIntc_ConfigTable[ ( unsigned portLONG ) XPAR_INTC_SINGLE_DEVICE_ID ];
-
-		pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
-		if( pxConfig->AckBeforeService & ( ulInterruptMask  ) )
-		{
-			XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
-			pxTablePtr->Handler( pxTablePtr->CallBackRef );
-		}
-		else
-		{
-			pxTablePtr->Handler( pxTablePtr->CallBackRef );
-			XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
-		}
-	}
+	/* Call the Xilinx interrupt handler provided by the OPB Interrupt Controller */
+	XIntc_DeviceInterruptHandler(0);
 }
 /*-----------------------------------------------------------*/